(1) Field of the Invention
The present invention relates to a method for making metal capacitors for integrated circuits, and more particularly relates to a method for making metal-insulator-metal (MIM) capacitor structures compatible with copper metallization schemes for wiring-up CMOS circuits. The MIM capacitors utilize the pad protect layer with copper (Cu) bottom electrodes and aluminum/copper (Al/Cu) top electrodes to achieve high capacitance per unit area while providing low series resistance resulting in a circuit having capacitors with high figure of merit Q.
(2) Description of the Prior Art
Capacitors on semiconductor chips are used for various integrated circuit applications. For example, these on-chip MIM capacitors can be used for mixed signal (analog/digital circuits) applications and radio frequency (RF) circuits. These capacitors can also serve as decoupling capacitors to provide improved voltage regulation and noise immunity for power distribution.
Typically these capacitors are integrated into the semiconductor circuit when the semiconductor devices are formed on the substrate. For example, the one or two doped patterned polysilicon layers used to make the field effect transistors (FETs) and/or bipolar transistors can also be used to form the capacitors. Alternatively, the capacitors can be fabricated using the multilevels of interconnecting metal patterns (e.g., Al/Cu) used to wire up the individual semiconductor devices (FETs).
In recent years portions of the AlCu metallization have been replaced with copper (Cu) to significantly reduce the resistivity of the conductive metal lines and thereby improve the RC (resistance×capacitance) delay time and improve circuit performance.
Generally the capacitors can be integrated into the circuit with few additional process steps. The capacitance C for the capacitor is given by the expressionC=eA/d where e is the dielectric constant, A is the capacitor area, and d is the thickness of the capacitor dielectric layer between the two capacitor electrodes. Typically the figure of merit Q for a capacitor in a circuit is Xc/R, where Xc is the capacitor reactance expressed in ohms, and R is the resistance (ohms) in series with the capacitance reactance. To improve the figure of merit it is desirable to maximize Xc while minimizing the R. In conventional capacitor structures multiple contacts are made to the relatively thin capacitor top metal (CTM) electrode to minimize resistance and improve the figure of merit Q. This is best understood with reference to FIG. 1. As shown in FIG. 1, when a more conventional MIM capacitor C is formed on the partially completed CMOS substrate 10, the CBM electrode is formed from an upper interconnecting metallurgy layer 15 of TiN/AlCu/TiN. An interelectrode dielectric layer 17 is formed on the CBM electrode top surface. A capacitor top metal (CTM) electrode is formed from a patterned relatively thin AlCu/TiN layer 19, and a planar insulating layer 21 is formed over the capacitor to insulate the capacitor and provide support for the next level of metal interconnections 25. A TiN/AlCu/TiN layer is then deposited and patterned to form the next level of metal interconnections. Vias (holes) 23 are etched in the insulating layer 21 to make contact to the CBM electrode 15 and the CTM electrode 19. Unfortunately, to minimize the series resistance R to the capacitor it is necessary to etch a series of closely spaced vias 23. For example, U.S. Pat. No. 5,926,359 to Greco et al., and U.S. Pat. No. 5,946,567, to Weng et al. are similar to the capacitor structure depicted above. In U.S. Pat. No. 5,406,447 to Miyazaki, a method is described for making an MOS, MIS, or MIM capacitor incorporating a high-dielectric material, such as tantalum oxide, strontium nitrate and the like, as the interelectrode dielectric layer. In U.S. Pat. No. 5,812,364 to Oku et al., a method is described for making a compatible MIM capacitor on a gallium arsenide substrate, but does not address the method of making MIM capacitors integrated with copper metallization schemes for CMOS devices on silicon substrates.
There is still a need in the semiconductor industry to form metal-insulator-metal (MIM) capacitors with high capacitance and low series resistance for improved figure of merit Q for advanced Cu metallization schemes on integrated circuits.